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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT238 3-to-8 line decoder/demultiplexer Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer FEATURES * Demultiplexing capability * Multiple input enable for easy expansion * Ideal for memory chip select decoding * Active HIGH mutually exclusive outputs * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT238 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled, QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT238 provide 8 mutually exclusive active HIGH outputs (Y0 to Y7). The "238" features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the "238" to a 1-of-32 (5 lines to 32 lines) decoder with just four "238" ICs and one inverter. The "238" can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. The "238" is identical to the "138" but has non-inverting outputs. TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay An to Yn E3 to Yn En to Yn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 16 17 3.5 72 18 20 21 3.5 76 ns ns ns pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer PIN DESCRIPTION PIN NO. 1, 2, 3 4, 5 6 8 15, 14, 13, 12, 11, 10, 9, 7 16 SYMBOL A0 to A2 E1, E2 E3 GND Y0 to Y7 VCC NAME AND FUNCTION address inputs enable inputs (active LOW) enable input (active HIGH) ground (0 V) outputs (active HIGH) positive supply voltage 74HC/HCT238 Fig.1 Pin configuration. Fig.2 Logic symbol. (a) (b) Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer 74HC/HCT238 Fig.4 Functional diagram. Fig.5 Logic diagram. FUNCTION TABLE INPUTS E1 H X X L L L L L L L L Note 1. H = HIGH voltage level L = LOW voltage level X = don't care X H X L L L L L L L L E2 X X L H H H H H H H H E3 X X X L H L H L H L H A0 X X X L L H H L L H H A1 X X X L L L L H H H H A2 L L L H L L L L L L L Y0 L L L L H L L L L L L Y1 L L L L L H L L L L L Y2 L L L L L L H L L L L OUTPUTS Y3 L L L L L L L H L L L Y4 L L L L L L L L H L L Y5 L L L L L L L L L H L Y6 L L L L L L L L L L H Y7 December 1990 4 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay An to Yn propagation delay E3 to Yn propagation delay En to Yn output transition time 47 17 14 52 19 15 50 18 14 19 7 6 max. 150 30 26 160 32 27 155 31 26 75 15 13 -40 to +85 min. max. 190 38 33 200 40 34 195 39 33 95 19 16 -40 to +125 min. max. 225 45 38 240 48 41 235 47 40 110 22 19 ns 74HC/HCT238 TEST CONDITIONS UNIT V WAVEFORMS CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 tPHL/ tPLH ns Fig.6 tPHL/ tPLH ns Fig.7 tTHL/ tTLH ns Figs 6 and 7 December 1990 5 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT238 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT An En E3 UNIT LOAD COEFFICIENT 0.70 0.40 1.45 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. typ. tPHL tPLH tPHL tPLH tPHL tPLH tTHL/ tTLH propagation delay An to Yn propagation delay An to Yn propagation delay E3 to Yn propagation delay E3 to Yn propagation delay En to Yn propagation delay En to Yn output transition time 21 17 22 18 21 18 7 max. 35 35 37 37 35 35 15 -40 to +85 min. max. 44 44 46 46 44 44 19 -40 to +125 min. max. 53 53 56 56 53 53 22 ns ns ns ns ns ns ns 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.6 Fig.6 Fig.6 Fig.7 Fig.7 Figs 6 and 7 UNIT V WAVEFORMS CC (V) TEST CONDITIONS December 1990 6 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer AC WAVEFORMS 74HC/HCT238 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7 |
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